// +build f303xe

// Peripheral: FMC_Bank2_3_Periph  Flexible Memory Controller Bank2.
// Instances:
//  FMC_Bank2_3  mmap.FMC_Bank2_3_R_BASE
// Registers:
//  0x00 32  PCR2  NAND Flash control register 2.
//  0x04 32  SR2   NAND Flash FIFO status and interrupt register 2.
//  0x08 32  PMEM2 NAND Flash Common memory space timing register 2.
//  0x0C 32  PATT2 NAND Flash Attribute memory space timing register 2.
//  0x14 32  ECCR2 NAND Flash ECC result registers 2.
//  0x20 32  PCR3  NAND Flash control register 3.
//  0x24 32  SR3   NAND Flash FIFO status and interrupt register 3.
//  0x28 32  PMEM3 NAND Flash Common memory space timing register 3.
//  0x2C 32  PATT3 NAND Flash Attribute memory space timing register 3.
//  0x34 32  ECCR3 NAND Flash ECC result registers 3.
// Import:
//  stm32/o/f303xe/mmap
package fmc

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	PWAITEN PCR2 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR2 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR2 = 0x01 << 3  //+ Memory type.
	PWID    PCR2 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	ECCEN   PCR2 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR2 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TAR     PCR2 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	ECCPS   PCR2 = 0x07 << 17 //+ ECCPS[1:0] bits (ECC page size).
)

const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)

const (
	IRS   SR2 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR2 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR2 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR2 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR2 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR2 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR2 = 0x01 << 6 //+ FIFO empty.
)

const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)

const (
	MEMSET2  PMEM2 = 0xFF << 0  //+ MEMSET2[7:0] bits (Common memory 2 setup time).
	MEMWAIT2 PMEM2 = 0xFF << 8  //+ MEMWAIT2[7:0] bits (Common memory 2 wait time).
	MEMHOLD2 PMEM2 = 0xFF << 16 //+ MEMHOLD2[7:0] bits (Common memory 2 hold time).
	MEMHIZ2  PMEM2 = 0xFF << 24 //+ MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time).
)

const (
	MEMSET2n  = 0
	MEMWAIT2n = 8
	MEMHOLD2n = 16
	MEMHIZ2n  = 24
)

const (
	ATTSET2  PATT2 = 0xFF << 0  //+ ATTSET2[7:0] bits (Attribute memory 2 setup time).
	ATTWAIT2 PATT2 = 0xFF << 8  //+ ATTWAIT2[7:0] bits (Attribute memory 2 wait time).
	ATTHOLD2 PATT2 = 0xFF << 16 //+ ATTHOLD2[7:0] bits (Attribute memory 2 hold time).
	ATTHIZ2  PATT2 = 0xFF << 24 //+ ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time).
)

const (
	ATTSET2n  = 0
	ATTWAIT2n = 8
	ATTHOLD2n = 16
	ATTHIZ2n  = 24
)

const (
	ECC2 ECCR2 = 0xFFFFFFFF << 0 //+ ECC result.
)

const (
	ECC2n = 0
)

const (
	PWAITEN PCR3 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR3 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR3 = 0x01 << 3  //+ Memory type.
	PWID    PCR3 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	ECCEN   PCR3 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR3 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TAR     PCR3 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	ECCPS   PCR3 = 0x07 << 17 //+ ECCPS[2:0] bits (ECC page size).
)

const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)

const (
	IRS   SR3 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR3 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR3 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR3 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR3 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR3 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR3 = 0x01 << 6 //+ FIFO empty.
)

const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)

const (
	MEMSET3  PMEM3 = 0xFF << 0  //+ MEMSET3[7:0] bits (Common memory 3 setup time).
	MEMWAIT3 PMEM3 = 0xFF << 8  //+ MEMWAIT3[7:0] bits (Common memory 3 wait time).
	MEMHOLD3 PMEM3 = 0xFF << 16 //+ MEMHOLD3[7:0] bits (Common memory 3 hold time).
	MEMHIZ3  PMEM3 = 0xFF << 24 //+ MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time).
)

const (
	MEMSET3n  = 0
	MEMWAIT3n = 8
	MEMHOLD3n = 16
	MEMHIZ3n  = 24
)

const (
	ATTSET3  PATT3 = 0xFF << 0  //+ ATTSET3[7:0] bits (Attribute memory 3 setup time).
	ATTWAIT3 PATT3 = 0xFF << 8  //+ ATTWAIT3[7:0] bits (Attribute memory 3 wait time).
	ATTHOLD3 PATT3 = 0xFF << 16 //+ ATTHOLD3[7:0] bits (Attribute memory 3 hold time).
	ATTHIZ3  PATT3 = 0xFF << 24 //+ ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time).
)

const (
	ATTSET3n  = 0
	ATTWAIT3n = 8
	ATTHOLD3n = 16
	ATTHIZ3n  = 24
)

const (
	ECC3 ECCR3 = 0xFFFFFFFF << 0 //+ ECC result.
)

const (
	ECC3n = 0
)
